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L6995S
STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION
1

FEATURES CONSTANT ON TIME TOPOLOGY ALLOWS OPERATION WITH LOWER DUTY THAN PWM TOPOLOGY VERY FAST LOAD TRANSIENTS 5V Vcc SUPPLY 1.5V TO 35V INPUT VOLTAGE RANGE 0.9V 1% VREF MINIMUM OUTPUT VOLTAGE AS LOW AS 0.9V SELECTABLE SINKING MODE LOSSLESS CURRENT LIMIT REMOTE SENSING OVP,UVP LATCHED PROTECTIONS 600A TYP QUIESCENT CURRENT POWER GOOD AND OVP SIGNALS PULSE SKIPPING AT LIGHT LOADS APPLICATIONS I/O BUS FOR CPU CORE SUPPLY NOTEBOOK COMPUTERS NETWORKING DC-DC DISTRIBUTED POWER
Figure 1. Package
TSSOP20
Table 1. Order Codes
Part Number L6995S L6995STR Package TSSOP20 Tape & Reel
2

3 DESCRIPTION The device is a step-down controller specifically designed to provide extremely high efficiency conversion, with losses current sensing tecnique. The "constant on-time" topology assures fast load transient response. The embedded "voltage feed-forward" provides nearly constant switching frequency operation. An integrator can be introduced in the control loop to reduce the static output voltage error. The available remote sensing improve the static and dynamic regulation recovering the wires voltage drop. Pulse skipping technique reduces power consumption at light load. Drivers current capability allows output current in excess of 20A.
Figure 2. Minimum Component Count Application
35V
Rin2 Rin1
5V
CIN
SHDN VCC
VDR
OSC BOOT HGATE
5V
C
HS
D
BOOT
BOOT
Vo
L
PHASE LGATE RILIM ILIM PGND LS
0.9V
COUT
DS
L6995S
SS
GND
NOSKIP VSENSE
CSS
INT VFB VREF
CVREF
April 2004
REV. 1 1/26
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Table 2. Absolute Maximum Ratings
Symbol VCC VDR VCC to GND VDR to GND HGATE and BOOT, to PHASE HGATE and BOOT, to PGND VPHASE PHASE LGATE to PGND ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF, INT, GNDSENSE to GND BOOT, HGATE and PHASE PINS OTHER PINS Ptot Tstg Power dissipation at Tamb = 25C Storage temperature range Maximum Withstanding Voltage Range Test Condition:CDF-AEC-Q100-002 "Human Body Model" Accepatance Criteria: "Normal Performance" Parameter Value -0.3 to 6 -0.3 to 6 -0.3 to 6 -0.3 to 42 -0.3-to 36 -0.3 to VDR+0.3 -0.3 to VCC+0.3 750 Unit V V V V V V V V
2000 1 -40 to 150
V W C
Table 3. Thermal Data
Symbol Rth j-amb Tj Parameter Thermal Resistance Junction to Ambient Junction operating temperature range Value 125 0 to 125 Unit C/W C
Figure 3. Pin Connection (Top View)
NOSKIP GNDSENSE INT VSENSE VCC GND VREF VFB OSC SS
1 2 3 4 5 6 7 8 9 10
TSSOP20
20 19 18 17 16 15 14 13 12 11
BOOT HGATE PHASE VDR LGATE PGND PGOOD OVP SHDN ILIM
Table 4. Pin Function
N 1 2 3 4 Name GNDSE NSE INT VSENS E Remote ground sensing pin Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the integrator in the control loop. If the integrator is not used, short this pin to VREF. This pin must be connected to the remote output voltage to detect overvoltage and undervoltage conditions and to provide integrator feedback input. Description NOSKIP Connect to VCC to force continuous conduction mode and sink mode.
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Table 4. Pin Function (continued)
N 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name VCC GND VREF VFB OSC SS ILIM SHDN OVP PGOOD PGND LGATE VDR PHASE HGATE BOOT IC Supply Voltage. Signal ground 0.9 V voltage reference. Connect max. a 10nF ceramic capacitor between this pin and ground. This pin is capable to source or sink up to 250uA PWM comparator feedback input. Short this pin to INT pin when using the integrator function, or to VSENSE pin without integrator. Connect this pin to the input voltage through a voltage divider in order to provide the feedforward function. It cannot be left floating. Soft start pin. A 5A constant current charges an external capacitor which value sets the softstart time. An external resistor connected between this pin and GND sets the current limit threshold. Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left floating. Open drain output. During the over voltage condition it is pulled up by an external resistor. Open drain output. During the soft start and in case of output voltage fault it is low. It is pulled up by external resistor. Low Side driver ground. Low Side driver output. Low Side driver supply. Return path of the High Side driver. High side MOSFETS driver output. Bootstrap capacitor pin. High Side driver is supplied through this pin. Description
Table 5. Electrical Characteristics (VCC = VDR = 5V; Tamb = 0C to 85C unless otherwise specified)
Symbol SUPPLY SECTION Vin VCC, VDR VCC Turn-onvoltage Turn-off voltage Hysteresis IqVDR IqVcc SHDN ISHVDR ISHVCC ISS Quiescent Current Drivers Device Quiescent current Device On Device Off Drivers shutdown current Devices shutdown current Soft Start current SS Clamp Voltage Soft start active range 400 SHDN to GND SHDN to GND VSS = 0.8V 4 4 450 500 10 VFB > VREF VFB > VREF 1.2 0.6 5 15 6 400 Input voltage range Vout=Vref Fsw=110Khz Iout=1A 1.5 4.5 4.2 4.1 100 20 600 35 5.5 4.4 4.3 V V V V mV A A V V A A A V mV Parameter Test Condition Min. Typ. Max. Unit
SHUTDOWN SECTION
SOFT START SECTION
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Table 5. Electrical Characteristics (continued) (VCC = VDR = 5V; Tamb = 0C to 85C unless otherwise specified)
Symbol Parameter ILIM input bias current Zero Crossing Comparator Offset Phase-gnd ON TIME Ton On time duration VREF=VSENSE OSC=250mV VREF=VSENSE OSC=500mV VREF=VSENSE OSC=1V VREF=VSENSE OSC=2V OFF TIME TOFFMIN Minimum off time KOSC/TOFFMIN VOLTAGE REFERENCE VREF Voltage Accuracy Input voltage offset IFB INT INT Input Bias Current Over Voltage Clamp Under Voltage Clamp Integrator Input Offset Voltage VSENSE-VREF IVSENSE Input Bias Current High side rise time High side fall time Low side rise time Low side fall time PGOOD UVP/OVP PROTECTIONS OVP UVP PGOOD PGOOD VPGOOD Over voltage threshold Under voltage threshold Upper threshold (VSENSE-VREF) Lower threshold (VSENSE-VREF) VSENSE rising VSENSE falling ISink=2mA with respect to VREF 112 66 107 86 115 69 110 89 0.14 118 72 113 92 0.2 % % % % V VDR=3.3V; C=7nF HGATE - PHASE from 1 to 3V VDR=3.3V; C=14nF LGATE from 1 to 3V GATE DRIVERS 50 50 50 50 70 70 70 70 ns ns ns ns VSENSE = VCC VSENSE = GND 1.04 0.82 -5 0.1 INTEGRATOR 1.07 0.84 1.1 0.86 5 V V mV A 0A < IREF < 100A 0.891 -2 0.1 0.9 0.909 +2 V mV A PWM COMPARATOR OSC=250mV 0.30 580 0.60 ns 850 470 250 130 950 520 285 160 1050 570 320 190 ns ns ns ns Test Condition RILIM = 2K to 400K Min. 4.9 -2 Typ. 5 Max. 5.1 2 Unit A mV CURRENT LIMIT AND ZERO CURRENT COMPARATOR
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5V
SHDN + VSENSE 1.15 VREF undervoltage comparator VSENSE 0.69 VREF S pgood comparators + VSENSE VCC VSENSE 0.89 VREF HGATE BOOT V(LGATE)<0.5V comp + LS and HS anti-cross-conduction comparators 1.10 VREF R +
PGOOD
OVP
overvoltage comparator VCC GND
SS
IC enable
5 uA
soft-start control
ILIM
power management
V IN
R level shifter V(PHASE)<0.2V comp Q HS driver
Figure 4. Functional & Block Diagram
positive current limit comparator
Toff min delay S
PHASE
V OUT
PHASE Ton min one-shot Q LS driver
+
VDR
0.2 R Ton one-shot
+
LGATE
VREF S VSENSE OSC
+
PGND
FB
-
pwm comparator
Ton= Kosc V(VSENSE)/V(OSC)
S Q
INT
+ -
Ton
one-shot
Gm
HS control
+ R
VREF
SENSEGND no-skip mode no-skip mode
Ton= Kosc V(VSENSE)/V(OSC)
OSC
bandgap -
PHASE
+
1.236V
VREF
0.9V
1.416
zero-cross comparator
Reference chain
NOSKIP
LS control
VSENSE
OSC
V IN
VREF VSENSE
L6995S
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4 DEVICE DESCRIPTION
4.1 Constant On Time PWM topology Figure 5. Loop block schematic diagram
Vin R1 One-shot generator OSC FFSR RQ HGATE Vref S Q LS DS
R2
Vsense
HS
Vout
+ PWM comparator FB
LGATE
R4
R3
The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time duration forced by the one-shot generator. The on time is directly proportional to VSENSE pin voltage and inverse to OSC pin voltage as in Eq1: Eq 1 V SENSE T ON = K OSC --------------------- + V
OSC
where KOSC = 250ns and is the internal propagation delay time (typ. 70ns). The system imposes in steady state a minimum on time corresponding to VOSC = 2V. In fact if the VOSC voltage increases above 2V the corresponding Ton will not decrease. Connecting the OSC pin to a voltage partition from VIN to GND, it allows a steady-state switching frequency FSW independent of VIN. It results: Eq 2 where Eq 3 V OSC R2 OSC = -------------- = -------------------V IN R2 + R 1 V OUT 1 OSC 1 f SW = -------------- ---------- = -------------- -------------- OSC = f SW K OSC OUT V IN T ON OUT K OSC
Eq 4
R4 V FB OUT = -------------- = -------------------V OUT R 3 + R4
The above equations allow setting the frequency divider ratio OSC once output voltage has been set; note that such equations hold only if VOSC<2V. Further the Eq2 shows how the system has a switching frequency ideally independent from the input voltage. The delay introduces a light dependence from VIN. A minimum off-time constrain of about 580ns is introduced in order to assure the boot capacitor charge and to limit the switching fre6/26
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quency after a load transient as well as to mask PWM comparator output against noise and spikes. The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity. 4.2 Closing the loop The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin is linked internally to the comparator negative pin and the positive pin is connected to the reference voltage (0.9V Typ.) as in Figure 2. When the FB goes lower than the reference voltage, the PWM comparator output goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise spike. After the on-time (calculated as described in the previous section) the system resets the flip-flop and then turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex logic than a flip-flop to manage the transition in correct way. For more details refers to the Figure 3. The voltage drop along ground and supply metals connecting output capacitor to the load is a source of DC error. Further the system regulates the output voltage valley value not the average, as in the Figure 5 is shown. So the voltage ripple on the output capacitor is a source of DC static error (as the PCB traces). To compensate the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 6. The internal integrator amplifier with the external capacitor CINT1 introduces a DC pole in the control loop. CINT1 also provides an AC path for output ripple. Figure 6. Valley regulation
Vout
DC Error Offset

Vref
Time
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance voltage in order to compensate the total static errors. A voltage clamper within the device forces INT pin voltage ranges from VREF-50mV, VREF+150mV. This is useful to avoid or smooth output voltage overshoot during a load transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peakto-peak amplitude is less than 150mV in steady state. In case of the ripple amplitude is larger than 150mV, a capacitor CINT2 can be connected between INT pin and ground to reduce ripple amplitude at INT pin, otherwise the integrator can operate out of its linear range. Choose CINT1 according to the following equation: Eq 5 g INT OUT C INT1 = -----------------------------2 Fu
where GINT=50 s is the integrator transconductance, OUT is the output divider ratio given from Eq4 and FU is the close loop bandwidth. This equation also holds if CINT2 is connected between INT pin and ground. CINT2 is given by:
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Eq 6 C INT2 V OUT --------------- = -----------------C INT1 V INT
Where VOUT is the output ripple and VINT is the ripple wanted at the INT pin (100mV typ). Figure 7. Integrator loop block diagram
Vin
R1 One-shot generator OSC FFSR RQ From Vsense Vref S Q LS FB DS LOAD HGATE PCB TRACES
R2
HS
Vout
+ PWM comparator Vref
LGATE
INT Cint2
+ +
Vsense
Gndsense
Integrator amplifier Cint1
Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hysteretic system the frequency can change with some parameters (input voltage, output current). In L6995S is implemented the voltage feed-forward circuit that allows constant switching frequency during steady-sate operation with the input voltage variation. There are many factors affecting switching frequency accuracy in steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver. Others related to the external components as high side MOSFET gate charge and gate resistance, voltage drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance. During a positive load transient, (the output current increases), the converter switches at its maximum frequency (the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output current decreases), the device stops to switch (high side MOSFET remains off). 4.3 Transition from PWM to PFM/PSK To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM mode essentially for the off section; the on section is the same. In PFM after a turn-on cycle the system turnson the low side MOSFET, until the inductor current reaches the zero A value, when the zero-crossing comparator turns off the low side MOSFET. In this way the energy stored in the output capacitor will not flow to ground, through the low side MOSFET, but it will flow to the load. In PWM mode, after a turn on cycle, the system keeps the low side MOSFET on until the next turn-on cycle, so the energy stored in the output capacitor will flow through the low side MOSFET to ground. The PFM mode is naturally implemented in hysteretic controller, in fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when the output voltage goes down a reference value. The device works in discontinuous mode at light load and in continuous mode at high load. The transition from PFM to PWM occurs when load current is around half the inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher the in-
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ductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the transient response is. In PFM mode the frequency changes, with the output current changing, more than in PWM mode; in fact if the output current increase, the output voltage decreases more quickly; so the successive turn-on arrives before, increasing the switching frequency. The PFM waveforms may appear more noisy and asynchronous than normal operation, but this is normal behaviour mainly due to the very low load. If the PFM is not compatible with the application it can be disabled connecting to VCC the NOSKIP pin. 4.4 Softstart If the supply voltages are already applied, the SHDN pin gives the start-up. The system starts with the high side MOSFET off and the low side MOSFET on. After the SHDN pin is turned on the SS pin voltage begins to increase and the system starts to switch. The softstart is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start range for the VSS voltage (where the output current limit increase linearly) starts from 0.6V to 1.5V. In this range an internal current source (5A Typ) charges the capacitor on the SS pin; the reference current (for the current limit comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5A (Typ.) when SS voltage is close to 1.5V and the maximum current limit is active. Undervoltage protection is disabled until SS pin voltage reaches 1.5V; instead the overvoltage is always present (see figure 7). Once the SS pin voltage reaches the 1.5V value, the voltage on SS pin doesn't impact the system operation anymore. If the SHDN pin is turned on before the supplies, the correct start-up sequence is the following: first turn-on the power section and after the logic section (VCC pin). Figure 8. Soft -Start Diagram
Vss
4.1V 1.5V
Soft-start active range 0.6V
Ilim current
5A
Time
Maximum current limit
Time
Because the system implements the soft start controlling the inductor current, the soft start capacitor selection is function of the output capacitance, the current limit and the soft start active range (VSS). In order to select the softstart capacitor it must be imposed that the output voltage reaches the final value before the soft start voltage reaches the under voltage value (1.5V). In other words the output voltage charging time has to be lower than the uvp time. The UVP time is given by: Eq 7 V uvp T uvp ( C SS ) = ----------- C SS Iss
In order to calculate the output volatge chargin time it should be calculated, before, the output volatrge function versus time. This function can be calculated from the inductor current function; the inductor current function can
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be supposed linear function of the time. Eq 8 ( R ilim /R dson K C I SS t ) I L ( t,C SS ) = ------------------------------------------------------------------( V SS C SS )
so the output voltage is given by: Eq 9 ( R ilim /R dson K C I SS t ) Q ( t,C SS ) V out ( t,C SS ) = ------------------------ = ---------------------------------------------------------------------C out ( C out V SS C SS 2 )
2
calling Vout as the Vout final value, the output charging time can be estimated as: Eq 10 ( V out C out V SS C SS 2 ) 0.5 I out ( C SS ) = --------------------------------------------------------------------------( R ilim /R dson K C I SS )
the minimum CSS value is given imposing this condition: Eq 11 Tout =Tuvp
4.5 Current limit The current limit comparator senses the inductor current through the low side MOSFET RDSON drop and compares this value with the ILIM pin voltage value. While the current is above the current limit value, the control inhibits the one-shot start. To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current depends on the inductor value, VIN VOUT and switching frequency. The average output current in current limit is given by: Eq 12 I OUT I = I max valley + ---2
CL
Thus, to set the current threshold, choose RILIM according to the following equation: Eq 13 R ILim I Lim I max valley = ---------------- --------Rds on 5.2
In current limit the system keeps the current constant until the output voltage meets the undervolatge threshold. The system is capable to sink current, but it has not a negative current limit. The system accuracy is function of the exactness of the resistance connected to ILIM pin and the low side MOSFET RDSON accuracy. Moreover the voltage on ILIM pin must range between 10mV and 2V to ensure the system linearity. Figure 9. Current limit schematic
To inductor LS
RILIM
PGN D
Current Comparator
PHASE
5A
Positive current limit
To logic
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4.6 Protection and fault Sensing VSENSE pin voltage performs output protection. The nature of the fault (that is, latched OV or latched UV) is given by the PGOOD and OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched: low side MOSFET is turned on, high side MOSFET is turned off and PGOOD goes low. In case the system detects an overvoltage the OVP pin goes high. To recover the functionality the device must be shut down and restarted thought the SHDN pin, or the supply has to be removed, and restart with the correct sequence. These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV fault). 4.7 Drivers The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching transition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the voltage on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage reaches 500mV. This is important since the driver can work properly with a large range of external power MOSFETS. The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the external power MOSFET gate charge and switching frequency. Eq 14 P driver = V cc Q gTOT F SW
The maximum gate charge values for the low side and high side are given from: Eq 15 f SW0 Q MAXHS = ------------ 75nC f SW f SW0 Q MAXLS = ------------ 125nC f SW
Eq 16
Where fSW0 = 500Khz. The equations above are valid for TJ = 150C. If the system temperature is lower the QG can be higher. For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation; in this case the maximum value is QMAXLS = 125nC. The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect. 5 APPLICATION INFORMATION
5.1 20A Demo board description The demoboard shows the device operation in general purpose applications. The evaluation board allows using only one supply because the on board linear regulator LM317LD; the linear regulator supplies the device through the J1. Output current in excess of 20A can be reached dependently on the MOSFET type. The SW1 is used to start the device (when the supplies are already present) and to select the PFM/PWM mode.
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Figure 10. Demoboard Schematic Diagram
5V
J1 R1
LM317LD
C1
VIN
R2 C5
R5 C2 R4
VCC VDR
R3 C13,14,15,16,17,18
OSC BOOT
C3
D1
C22 HGATE Q1,2,3, C19
R6
R7
PHASE PGOOD OVP LGATE Q4,5,6
Vout L
D2
R9 LOAD C7,8,9,10,11,12
L6995S
ILIM C21 PGND GND NOSKIP VSENSE GNDSENSE SS
R8
R10
5V
R11 Without Int. R13
C20
R12
C4
INT VFB SHDN VREF With Int. Without Int. With Int
C23
C24
5V
Rn C6 C7 Rn
5.2 Jumper Connection Table 6. Jumper connection with integrator
Component C4 C7 INT NOINT Connection Mounted Mounted * Close Open
* This component is not necessary, depends from the output ESR capacitor. See the integrator section.
Table 7. Jumper connection without integrator
Component C4 C7 INT NOINT Connection Not mounted Not Mounted Open Close
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5.3 NOTE There is a linear regulator on board, it allows to use one generator (only for the power section, in fact the IC section is powered by the linear regulator); if the regulator is used close the J1, other wise it has to keep open. Be careful measuring the efficiency with the linear regulator asserted. At high current in the integrator configuration (around 20A), it can be seen an oscillation in the switching frequency due to the noise interaction, to reduce this oscillation put a noise filter RN, CN like in the figure 9. Note the RN resistor is in the place of the INT jumper near C4. RN, CN, should be selected with a pole frequency around 1Mhz, but anyway higher than switching frequency (five times). 5.4 DEMOBOARD LAYOUT Real dimensions: 5,7 cm X 7,7 cm (2,28inch X 3, 08inch) Figure 11. PCB layout: bottom side Figure 13. Internal ground plane
Figure 12. PCB Layout: Top side
Figure 14. Power & signal plane
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Table 8. PCB Layout guidelines
Goal Low radiation and low magnetic coupling with the adjacent circuitry. Suggestion 1) Small switching current loop areas. (For example placing CIN, High Side and Low side MOSFETS, Shottky diode as close as possible). 2) Controller placed as close as possible to the power MOSFET. 3) Group the gate drive component (Boot cap and diode together near the IC. Keep power traces and load connections short and wide. Phase pin and PGND pin must be made with Kelvin connection and as close as possible to the Low Side MOSFETS. 1) Put the feedback component (like output divider, integrator network, etc) as close as possible to the IC. 2) The feedback traces must be parallel and as close as possible. Moreover they must be routed as far as possible from the switching current loops. 3) Make the controller ground connection like the figure 19.
Don't penalty the efficiency. Ensure high accuracy in the current sense system. Reduce the noise effect on IC.
Table 9. Component list The component list is shared in two sections: the first for the general-purpose component, the second for power section: GENERAL-PURPOSE SECTION
Part name RESISTOR R1 R2 R3 R4 R5 R6, R7, R11, R12 R8 R9 R10 R13 CAPACITOR C1 C2 C3 C4 C5 C6 C7 C19 C20 220nF 47F 220nF 330pF 47pF 10nF N.M. 220nF 220nF 0805 KEMET-16V 0805 0603 0603 0603 0603 0805 0603 Softstart capacitor Second integrator capacitor First integrator capacitor 100 300 560k 33k 47 33k 47k 390 1K 220 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 Current limit resistor (To set current limit) Output resistor divider (To set output voltage) Input resistor divider (To set switching frequency) Output resistor divider for the linear regulator. Value Dimension Notes
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Part name C21 C22 C23 C24 C25 DIODES D1 BAT54 25V 1nF 1uF Value 47pF 220nF Dimension 0603 0805 0603 0603 Tantalum N.M. Notes
POWER SECTION
OUTPUT CAPACITORS C10-C11-C12 INPUT CAPACITORS C13, C14, C16, C17, C15 C18 10uF 10uF Part name Value 10uF 10uF INDUCTOR L1 0.6H 0.6H 0.6H 0.6H POWER MOS Q1,Q2 Q5,Q6 DIODES D2 INTEGRATED CIRCUIT U1 U2 Switcher
Notes: 1. N.M.=Not Mounted 2. The demoboard with this component list is set to give: VOUT = 1.25V, FSW = 270kHz with an input voltage around VIN = 20V with the integrator feature, and with 20A continuos output current. 3. All capacitors are intended ceramic type otherwise specified.
3X330uF
EEFUE0D331R PANASONIC C34Y5U1E106Z TOKIN C3225Y5V1E106Z TDK Dimension ECJ4XF1E106Z PANASONIC TMK325F106ZH TAIYO YUDEN ETQP6F0R6BFA PANASONIC A959ASR60N TOKO DXM1306-R60-T COEV CEP12D38H0R6 SUMIDA STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics
Output capacitor C8, C9 N.M.
Input capacitor
Notes
STS11NF3LL STSJ25NF3LL STS25NH3LL STPS3L40U LM317LD L6995S
Q3 N.M. Q3 N.M. Q4 N.M. 25V Linear regulator
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6 STEP BY STEP DESIGN
VIN = 20V VOUT = 1.25V IOUT = 20A FSW = 270kHz In this design it is considered a low profile demoboard, so a great attention is given to the components height. 6.1 Input capacitor. A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC component of this current is quite high and dissipates a considerable amount of power on the ESR capacitor: Eq 17
2 Vin ( Vin - Vout ) P CIN = ESR CIN Iout ----------------------------------------------2 Vin
The IRMS current is given by: Eq 18 Icin rms =
2 2 Iout ( 1 - ) + ----- ( I L ) 12
Neglecting the last term, the equation reduces to: Eq 19 Icin rms = Iout ( 1 - )
which maximum value corresponds to = 1/2. ICINRMS, has a maximum equal to = 1/2 (@ VIN = 2xVOUT, that is, 50% duty cycle). The input capacitor, therefore, should be selected with an RMS rated current higher than ICINRMS. Electrolytic capacitors are the most used because are the cheapest ones and are available with a wide range of RMS current ratings. The only drawback is that, considering a requested ripple current rating, they are physically larger than other capacitors. Very good tantalum capacitors are coming available, with very low ESR and small size. The only problem is that they occasionally can burn out if subjected to very high current during the charge. So, it is better avoid this type of capacitors for the input filter of the device. In fact, they can be subjected to high surge current when connected to the power supply. If available for the requested value and voltage rating, the ceramic capacitors have usually a higher RMS current rating for a given physical size (due to the very low ESR). From the equation 18 it is found: Icinrms = 4.8A Considering 10F capacitors ceramic, that have ICINRMS =1.5A, 6 pzs. are needed. 6.2 Inductor In order to determine the inductor value is necessary considering the maximum output current to decide the inductor current saturation. Once the inductor current saturation it is found automatically is found the inductor value. In our design it is considered a very low profile inductor. L = 0.6H The saturation current for this choke is around 25A 6.3 Output capacitor The output capacitor is chosen by the output voltage static and dynamic accuracy. The static accuracy is related to the output voltage ripple value, while the dynamic accuracy is related to the output current load step. If the static precision is around 2% for the 1.25V output, the output accuracy is 25mV. To determine the ESR value from the output precision is necessary before calculate the ripple current:
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Eq 20 Vin - Vo Vo I = ---------------------- -------- T sw L Vin
Considering a switching frequency around 270kHz from the equation above the ripple current is around 7A. So the maximum ESR should be: Eq 21 V ripple ESR = -------------------- = 7m I ---2
The dynamic specifications are sometimes more relaxed than the static requirements so the ESR value around 7m should be enough. The current ripple flows through the output capacitor, so the output capacitors should be calculated also to sustain this ripple: the RMS current value is given from Eq22. Eq 22 1 Icout rms = ---------- I L 23
But this is usually a negligible constrain when choosing output capacitor. To allow the device control loop to work properly output capacitor zero should be at the least ten times smaller than switching frequency. The output capacitor value (COUT) and the output capacitor ESR (ESROUT) should be large enough and small enough, to keep the output voltage ripple within the specification and to give to the device a minimum signal to noise ratio.
6.4 Power MOSFETS and Schottky Diodes Since a 5V bus powers the gate drivers of the device, the use of logic-level MOSFETS is highly recommended, especially for high current applications. The breakdown voltage VBRDSS must be greater than VINMAX with a certain margin. The RDSON can be selected once the allowable power dissipation has been established. By selecting identical Power MOSFET for the main switch and the synchronous rectifier, the total power they dissipate does not depend on the duty cycle. Thus, if PON is this power loss (few percent of the rated output power), the required RDSON (@ 25 C) can be derived from: Eq 23 P ON RDS ON = -----------------------------------------------2 Iout ( 1 + T )
is the temperature coefficient of RDSON (typically, = 510-3 C-1 for these low-voltage classes) and T the admitted temperature rise. It is worth noticing, however, that generally the lower RDSON, the higher is the gate charge QG, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge QG moves from the input source to ground, resulting in an equivalent drive current: Eq 24 Iq = Qg FSW
For application with low Duty Cycle, where the input voltage is high (around 20V) it is very important to select the high side MOSFET with low gate charge, to reduce the switching losses as STS11NF3LL. For the low side section should be selected a low RDSON as STS25NH3LL. A SCHOTTKY diode can be added to increase the system efficiency at high switching frequency (where the dead times could be an important part of total switching period). This optional diode must be placed in parallel to the synchronous rectifier must have a reverse voltage VRRM greater than VINMAX. The current size of the diode must be selected in order to keep it in safe operating conditions.
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6.5 Output voltage setting To select the output divider network there isn't a specific criteria, but a low divider network value (around 100) reduces the efficiency at low current; instead a high value divider network (500K) increase the noise effects. A network divider values from 1K to 50K is right. From the Eq4: R10 = 1K R9 = 390 The device output voltage is adjustable by connecting a voltage divider from output to VSENSE pin. Minimum output voltage is VOUT = VREF = 0.9V. Once output divider and frequency divider have been designed as to obtain the required output voltage and switching frequency, the following equation gives the smallest input voltage, which allows L6995S to regulate (which corresponds to TOFF = TOFF, MIN): Eq 25 OSC 1 < 1 - -------------- ---------------------------- OUT K OSC ----------------------- T OFFMIN
where the KOSC/TOFFMIN ratio worst-case is given in electrical characteristic table (pag. 4). 6.6 Voltage Feed Forward Choosing the switching frequency around 270KHz from the Eq1. It can be selected the input divider. For example: R3=560K R4=28K In order to compensate the comparator delay R4 resistor should be increased around 20%. R4=33K 6.7 Current limit resistor From the Eq13 can be set the valley current limit, knowing the low side RDSON. To set the exact current limit it must be considered the temperature effect. So two STS25NH3LL have 2.75m @ 25C, at 100C can be considered 3.85m. R8 = 47K 6.8 Integrator capacitor Let it be FU = 15kHz. Since VREF = 0.9V, from Eq4, it follows OUT = 0.72 and, from Eq5 it follows CINT1 = 330pF. Because the ripple is lower than 150mV the system doesn't need the second integrator capacitor. 6.9 Soft start capacitor Considering the soft start equations (Eq. 11) at page 10, it can be found: CSS = 200pF These equations are valid whitout load. When an active load is present the equantions result more complex; further some active loads have unexpected effect, as higher current than the expected one during the start up, that can change the start up time. In this case the capacitor value can be selected on the application; anyway the Eq11 gives an idea about the CSS value.
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6.9.1 Efficiency VIN = 20V VOUT = 1.25V FSW = 270KHz Figure 15. Efficiency vs output current
Ef f [ %]
85
80
75
70
65
60 0,0 4,0 8,0 1 2,0 16 ,0 20 ,0 24 ,0
Cu r r e n t [A]
V in=20 V V o u t=1.25 V Fsw =22 0Khz PFM V in=20 V V o ut=1 .25 V Fs w =22 0K hz PW M
6.10 5A demo Board Figure 16. Schematic Diagram
Vcc
R7
C8
R6
J1
C7,C13 VIin
R4 OSC BOOT C4 HGATE R5 TP1 PGOOD OVP TP2 ILIM R8 C12 LGATE Q2 D2 R1 R10 PHASE Q1 D1 L1 VCC VDR
C11 C10
GNDin
VOUT
R3 C14,C15 R2
L6995S
U1
PGND GND NOSKIP VSENSE GNDOUT
GNDSENSE SS C9 R9 INT VFB SHDN SD TP3 C5 VREF C6 NOINT C2 NS Cn Rn NOINT INT C1 INT C3
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6.11 DEMOBOARD LAYOUT Real dimensions: 4.7 cm X 2.7 cm (1.85inch X1.063inch) Figure 17. Top side components placement Figure 19. Top side layout
Figure 18. Bottom side Jumpers distribution
Figure 20. Bottom side layout
Table 10. Component list GENERAL-PURPOSE SECTION
Part name RESISTOR R1, R5, R9, R10 R2 R3 R4 R6 R7 R8 CAPACITOR C1 C2 C3 C4 C5 C6 C8, C12 C9 Value 33k 10k 10k 21k 470k 47 120k 330pF N.M. N.M. 100nF 1F 10nF 47pF 22nF Dimension 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 Tantalum 0603 0603 0603 Notes Pull-up resistor Output resistor divider (To set output voltage) Input resistor divider (To set switching frequency)
Current limit resistor First integrator capacitor Second integrator capacitor N.M.
Softstart capacitor
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Part name C10 C11 DIODE D1 INPUT CAPACITORS C7, C13 OUTPUT CAPACITORS C14, C15 INDUCTOR L1 Value 100nF 100nF BAR18 Dimension 0603 0603 Notes
POWER SECTION
10F 330F C34Y5U1E106ZTE12 TOKIN EEFUE0D331R PANASONIC DO3316P-272HC COILCRAFT ETQP6H2R2GF PANASONIC DQ7545 COEV STMicroelectronics STMicroelectronics Dual MOSFETS in single package
3
2.7H 2.2H 3.3H
POWER MOS Q1,Q2 DIODE D2
STS8DNF3LL STPS3L40U
Notes: 1. N.M.=Not Mounted 2. The demoboard with this component list is set to give: VOUT = 1.8V, FSW = 250kHz with an input voltage around VIN = 20V and with the integrator feature. 3. The diode efficiency impact is very low; it is not a necessary component. 4. All capacitors are intended ceramic type otherwise specified.
6.11.1Efficiency Vin = 20V Vout = 1.8V Fsw = 270kHz Figure 21. Efficiency vs output current
Ef f [ %]
90
80
70
60
50
40
30 0,0 0,5 1 ,0 1,5 2,0 2,5 3,0 3,5 4,0 4,5 5,0 5 ,5 6,0
Cu r r e n t [A]
V in=20V V ou t=1.8V Fs w =270K hz PW M V in=2 0V V out=1 .8V Fs w =2 70Khz PFM
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7 TYPICAL OPERATING WAVEFORMS
The measurements refer to the part list in table 4. Vin = 20V Vout = 1.25V Fsw = 270kHz Tamb = 25C. Figure 22. Soft Start with no load. Figure 24. Normal functionality in PSK mode.
Ch1-> Inductor current Ch2-> Output voltage
Ch1-> Inductor current Ch2-> Output voltage Ch3-> Phase voltage
Figure 23. Soft Start with 20A load.
Figure 25. Normal functionality in PWM mode.
Ch1-> Inductor current Ch2-> Output voltage Ch3-> Soft Start voltage
Ch1-> Inductor current Ch2-> Output voltage Ch3-> Phase voltage
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Figure 26. Load transient from 0 to 18A. Figure 28. Switching Frequency Vs Output current
Fsw [ Khz]
350 300 250 200 150 100 50 0 5 10 15
V in [ V ] P SK/P FM P WM
20
25
Ch1-> Output current Ch2-> Output voltage Ch3->Phase voltage
Figure 27. Load transient from 18A to 0A..
Figure 29. Switching Frequency Vs Input Voltage
Fsw [ K h z] 3 50 3 00 2 50 2 00 150 100 50 0
PFM PW M
Ch1-> Output current Ch2-> Output voltage Ch3->Phase voltage
0 ,0
5 ,0
1 0,0
1 ,0 5
2 0,0
25 ,0
C u rre n t [ A ]
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Figure 30. TSSOP20 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 b c D (1) E 0.050 0.800 0.190 0.090 6.400 6.200 6.500 6.400 4.400 0.650 0.450 0.600 1.000 0 (min.) 8 (max.) 0.100 0.004 0.750 0.018 1.000 TYP. MAX. 1.20 0.150 1.050 0.300 0.200 6.600 6.600 4.500 0.002 0.031 0.007 0.004 0.252 0.244 0.170 0.256 0.252 0.173 0.026 0.024 0.039 0.030 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.008 0.260 0.260 0.177 inch
OUTLINE AND MECHANICAL DATA
E1 (1) 4.300 e L L1 k aaa
TSSOP20
Thin Shrink Small Outline Package
Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side.
0087225 (Jedec MO-153-AC)
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Table 11. Revision History
Date April 2004 Revision 1 First Issue Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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